1. Field of the Invention
The present invention relates to a semiconductor memory device comprising a plurality of banks and having redundant word lines and redundant bit lines.
2. Description of the Related Art
If the memory cells of a particular memory cell array become defective in a semiconductor memory device having a plurality of memory cell arrays, the functions of the defective memory cells are compensated for by replacing the rows including the defective memory cells by a redundant memory cell array that has been prepared in advance.
FIG. 1 is a block diagram showing the configuration of such a semiconductor memory device of the prior art. This prior-art semiconductor memory device comprises four memory cell plates. The memory cell plates comprises normal memory cell arrays 11A.sub.1, 11A.sub.2, 11A.sub.3, and 11A.sub.4, and redundant memory cell arrays 13A.sub.1, 13A.sub.2, 13A.sub.3, and 13A.sub.1, respectively. In the prior-art example, moreover, a shared sense amplifier system is employed wherein sense amplifiers 15A.sub.1, 15A.sub.2, 15A.sub.3, 15A.sub.4, and 15A.sub.8 are shared by the memory cell plates from left to right.
In addition, reading and writing of data is carried out in each of the memory cell plates by means of redundant word line drivers 14A.sub.1 -14A.sub.4, normal row decoders 12A.sub.1 -12A.sub.4, and redundant row address judging circuits 16A.sub.1 -16A.sub.4.
Normal row decoders 12A.sub.1 -12A.sub.4 activate address word lines designated by address signals 21.
When redundant row selection signals 22A.sub.1 -22A.sub.4 become active, respective redundant word line drivers 14A.sub.1 -14A.sub.4 activate word lines connected to redundant memory cell arrays 13A.sub.1 -13A.sub.4.
The addresses of memory cells judged to be defective are programmed in advance, and when addresses designated by address signal 21 match these programmed addresses, redundant row address judging circuits 16A.sub.1 -16A.sub.4 activate redundant row selection signals 22A.sub.1 -22A.sub.4, respectively.
Although signals other than address signals 21 are inputted to redundant row address judging circuits 16A.sub.1 -16A.sub.4, such signals are here omitted in the interest of simplifying the explanation.
The circuit diagram of redundant row address judging circuit 16A.sub.1, will next be explained with reference to FIG. 2.
Redundant row address judging circuit 16A.sub.1 comprises n-channel MOSFETs 42.sub.1 -42.sub.9, fuse elements 43.sub.1 -43.sub.9, p-channel MOSFET 31, inverter 33, p-channel MOSFET 32, n-channel MOSFET 34A, p-channel MOSFET 37A, and inverters 35A and 36A.
Complementary address signals 41.sub.1 -41.sub.9 are connected to the gates of n-channel MOSFETs 42.sub.1 -42.sub.9, respectively. Complementary address signals 41.sub.1 -41.sub.9 are signals comprises row addresses designated by address signal 21 and signals in which each of the bits of row addresses are inverted.
Fuse elements 43.sub.1 -43.sub.9 are provided between node 54 and each of n-channel MOSFETs 42.sub.1 -42.sub.9 and are opened by cutting with a laser beam. P-channel MOSFET 31 turns ON and precharges node 54 when redundant row address judging circuit precharge signal 51 becomes active.
Inverter 33 and p-channel MOSFET 32 both hold the potential of node 54 at a stable level and invert the potential of node 54 and output the result.
N-channel MOSFET 34A turns ON when redundant row selection signal latch circuit 52A becomes active and inputs the output of inverter 33 to inverter 35A.
P-channel MOSFET 37A precharges the input of inverter 35A when redundant row selection signal precharge signal 53A becomes active.
Inverters 35A and 36B both hold the potential transferred by means of n-channel MOSFET 34A and invert the potential and output the result as redundant row selection signal 22A.sub.1.
Explanation will next be presented regarding the operation of the prior-art semiconductor memory device with reference to FIG. 1 and FIG. 2.
First, if a particular defective memory cell is discovered in the wafer inspection process of a semiconductor memory device, the necessary elements of fuse elements 43.sub.1 -43.sub.9 are cut based on the row address of the address of the defective memory cell and a signal in which each bit of the row address is inverted, thereby programming and storing the addresses of defective memory cells.
Regarding the operation in a case in which defective memory cells are replaced by redundant memory cells, redundant row address judging circuit precharge signal 51 and redundant row selection signal precharge signal 53A first become active, and node 54 and the input of inverter 35A are precharged to a fixed voltage.
Then, if complementary address signals 41.sub.1 -41.sub.9 are the same as row addresses that have been programmed in advance, node 54, which has been charged in advance by pchannel MOSFET 31, remains at the precharged voltage without discharging because the fuse elements of corresponding addresses have been cut. Redundant row selection signal 22A.sub.1 is then activated by the activation of redundant selection signal latch signal 52A, whereby redundant word line driver 14A.sub.1 is activated and the word line connected to redundant memory cell array 13A.sub.1 becomes active. Although not shown in the figure, the normal word line is simultaneously deactivated.
Operations for reading and writing data are carried out as usual at redundant row address judging circuit 16A.sub.1 if the row addresses designated by inputted address signal 21 do not match with the pre-programmed row addresses. In such a case, any of normal row decoders 12A.sub.1 -12A.sub.4 operates in accordance with the row addresses designated by address signals 21, and the normal word lines of any of normal memory cell arrays 11A.sub.1 -11A.sub.4 become active.
Redundant row address judging circuits 16A.sub.2 -16A.sub.4 operate in the same way as redundant row address judging circuit 16A.sub.1 and explanation of their operation is therefore omitted.
In this semiconductor memory device of the prior art, the normal word lines that can be replaced by redundant row address judging circuits 16A.sub.1 -16A.sub.4 are not limited to those of just one memory cell plate, but can be the normal word lines of any memory cell plate of the four memory cell plates. For example, if the address of normal memory cell array 11A.sub.2 is programmed at redundant row address judging circuit 16A.sub.1, a normal word line of normal memory cell array 11A.sub.2 can be replaced by redundant memory cell array 13A.sub.1 by redundant row address judging circuit 16A.sub.1.
Redundant row address judging circuits 16A.sub.1 -16A.sub.4 can therefore replace the normal word lines of any memory cell plate, resulting in a redundancy configuration having four redundant word lines for every four plates. As a result, four defective memory cells can all be replaced even if the four defective memory cells are concentrated in one particular memory cell plate. This method therefore has a replacement efficiency that is higher than a redundancy configuration that does not adopt this method and has just one redundant word line per plate. This method is particularly effective in cases in which the occurrence of defective memory cells is biased.
In a semiconductor memory device constructed from a plurality of memory cell plates according to the prior art, an interleaved operation is carried out to enable rapid access of data by dividing the plurality of memory cell plates into a plurality of banks, which are the units by which data are accessed. Explanation will next be presented regarding a case in which redundant memory cells are provided in a semiconductor memory device configured in this way.
FIG. 3 is a block diagram of a semiconductor memory device having a two-bank configuration, which is one example of this type of the prior art. Of the four memory cell plates of FIG. 3, the two plates on the left are allotted to bank A and the two plates on the right side are allotted to bank B. In other words, bank A comprises normal memory cell arrays 11A.sub.1 and 11A.sub.2 and redundant memory cell arrays 13A.sub.1 and 13A.sub.2, and bank B comprises normal memory cell arrays 11B.sub.1 and 11B.sub.2 and redundant memory cell arrays 13B.sub.1 and 13B.sub.2. Since normal memory cell arrays 11A.sub.2 and 11B.sub.1 belong to different banks, the word lines of each can be selected simultaneously. As a result, these two normal cell arrays cannot share a common sense amplifier, and sense amplifiers 15A.sub.9 and 15B.sub.1 are therefore provided for the respective memory cell plates.
In this semiconductor memory device of the prior art, redundant row address judging circuit 16A.sub.1 can replace only the word lines of either normal memory cell array 11A.sub.1 or 11A.sub.2 of bank A. This is because problems occur if redundant memory cell array 13A.sub.1 is addressed with a particular word line of normal memory cell array 11B.sub.1 of bank B using redundant row address judging circuit 16A.sub.1. Such problems occur because there are cases in which normal memory cell array 11A.sub.1 and redundant memory cell array 13A.sub.1, which share the use of sense amplifier 15A.sub.1, are simultaneously active when a memory cell of normal memory cell array 11A.sub.1 is selected.
Therefore, when a semiconductor memory device having the same memory cell array configuration as shown in FIG. 1 is divided between two banks as shown in FIG. 3, the memory cell plates that can be replaced by one redundant row address judging circuit are reduced by half. As a consequence, a semiconductor memory device of the configuration shown in FIG. 3 has a redundancy configuration with two redundant word lines for every two plates, and this configuration results in a drop in the replacement efficiency compared with a redundancy configuration having four redundant word lines for every four plates as shown in FIG. 1.
In other words, when the prior-art method is applied to a semiconductor memory device as described hereinabove whereby a bank configuration is adopted that can independently access row addresses in the interior and simultaneously select a plurality of word lines as in, for example, synchronous DRAM, the redundant replacement region is divided in accordance with the provision of a plurality of banks, and redundancy judging and replacement must be performed independently at each bank, thereby decreasing the replacement efficiency.
This problem can be solved by increasing the number of redundant memory cell arrays or providing redundant row address judging circuits for each bank. However, in the current state of the art of LSI fabrication, there are physical limits to the dimensions of fuse elements because fuse elements are cut by laser beams. Fuse elements consequently cannot be scaled and reduced in proportion to the wiring or transistors. In actuality, therefore, the number of fuse elements that can be provided on a 256-Mbit DRAM is limited by the size of the chip, and the number of redundant row address judging circuits cannot be increased.
A method is disclosed in Japanese Patent Laid-open No. 7(1995)-176200 for raising replacement efficiency without bringing about an increase in chip area as described hereinabove. A semiconductor memory device in which this prior-art configuration is applied to a two-bank configuration having two memory plates in one bank will next be described with reference to FIG. 4.
In addition to the semiconductor memory device shown in FIG. 3, the semiconductor memory device of the prior art shown in FIG. 4 provides redundant memory cell arrays 13B.sub.1 -13B.sub.4 for each memory plate, with two redundant memory cell arrays for each memory plate. In addition, redundancy word line drivers 14B.sub.1 -14B.sub.4 are provided for redundant memory cell arrays 13B.sub.1 -13B.sub.4, respectively. Finally, redundant line selection signals 22A.sub.1 -22A.sub.4 are inputted to redundant word line drivers 14B.sub.1 -14B.sub.4, respectively.
In this semiconductor memory device of the prior art, word lines of the memory plate of bank A can be replaced if redundant row address judging circuit 16A.sub.1 uses redundant memory cell array 13A.sub.1, and word lines of the memory cell plate of bank B can be replaced if redundant memory cell array 13B.sub.1 is used. As a result, in a semiconductor memory device of two-bank configuration, the same replacement efficiency can be obtained with just four redundant row address judging circuits as for a redundancy configuration having four redundant word lines for each four plates.
However, in a case in which redundant row address judging circuit 16A.sub.1 in this semiconductor memory device of the prior art replaces the word lines of a particular row address in bank A with redundant memory cell array 13A.sub.1, redundant memory cell array 13B.sub.1 forcibly replaces the word line at that row address of bank B.
Ordinarily, normal memory cell arrays 11A.sub.1, 11A.sub.2, 11B.sub.1, and 11B.sub.2 are inspected by, for example, an operation check, but no inspections such as operation checks are performed for redundant memory cell arrays 13A.sub.1 -13A.sub.4 and 13B.sub.1 -13B.sub.4, with the result that memory word lines that are not defective are needlessly replaced with still unchecked redundant memory cell arrays.